1. Field of the Invention
The present invention concerns a packet forwarding system to transfer packets through a plurality of interfaces by reading out information for the packet forwarding beforehand and a method thereof.
2. Description of the Related Art
FIG. 1 is a schematic block diagram of a conventional packet forwarding system. Referring to FIG. 1, the packet forwarding system includes a packet processor 110, a controller 130, a transmit (TX) queue 150, a packet memory 160, and an interface part 170.
The packet processor 110 organizes incoming data into a suitable data unit (for example, an asynchronous transfer mode (ATM) cell) and generates an Internet protocol (IP) packet. The IP packet is organized into at least one subpacket of a fixed length. The subpackets (hereinafter, referred to as packet data) are stored in the packet memory 160.
The TX queue 150 buffers information including location information of the packet data for packet forwarding in sequential order starting from a head entry pointed to by a head pointer to a tail entry pointed to by a tail pointer, and operates in a first-in first-out (FIFO) process.
The TX queue 150 has a space to record information to transfer the packets including the location information of the IP packets of a maximum number M. The controller 130 transfers, through the interface part 170, the IP packets stored in the packet memory 160 based on the location information of the IP packets of the TX queue 150.
That is, the controller 130 controls the TX queue 150 to read out the packet data from the packet memory 160, and controls the packet memory 160 to transfer the packets to a destination in a predetermined order through the interface part 160.
In general, the storage medium of the TX queue 150 is a static random access memory (SRAM) having a high performance with respect to random operation. The storage medium of the packet memory 160 is a dynamic random access memory (DRAM) having a high performance with respect to burst operation.
Recently, the packet forwarding system for network devices such as routers, switches, and gateways, has been frequently utilized to transfer packets to diverse destinations through a plurality of output ports, that is, a plurality of interfaces.
Thus, packet information needs to be managed, that is, information for packet forwarding, such as information on the interface transferring the packets as well as the location information of the stored packet data and the information on the order of the packet forwarding. The TX queue 150 is used to manage the packet information.
In addition to the packet forwarding through the interfaces using the single TX queue 150, the packets may be transferred using a plurality of TX queues each for the plurality of the interfaces.
FIG. 2 illustrates packet forwarding using a single TX queue. Referring to FIG. 2, the packet processor 210 organizes data into packets, stores the packet data into the packet memory (not shown), and stores the information on the forwarding of the stored packets, that is, the packet information to the TX queue 250.
The TX queue 250 enqueues the information on the packet forwarding in order starting from the head entry pointed by the head pointer to the tail entry pointed by the tail pointer, and operates in the FIFO process. Hence, the packets are processed in order of the queue of the TX queue 250. That is, if the prior packet is not processed, the posterior packet is not processed as well.
The single TX queue 250 operating in the FIFO process manages the information of the packets transferred through the plurality of the interfaces 270-1 to 270-N of the interface part 270. If the packets are not transferred due to problems or congestion in the first interface 270-1, the second interface 270-2 cannot transfer the packet, and even if it is possible, since the second interface 270-2 cannot receive the information for the packet, forwarding from the TX queue 250 cannot take place. This disadvantage of packet forwarding using the single TX queue 250 is called ‘head of line blocking’.
FIG. 3 illustrates packet forwarding using each of the plurality of the TX queues for the interface. Referring to FIG. 3, the plurality of the TX queues 350-1 to 350-N of the TX queue part 350 corresponds to the plurality of the interfaces 370-1 to 370-N of the interface part 370. Each TX queue 350-1 to 350-N has the same construction as the single TX queue 250 (FIG. 2), and operates independently. Hence, ‘head of line blocking’, the disadvantage of the single TX queue, does not arise.
However, the TX queues 350-1 to 350-N each have the space to record the information for packet forwarding, including the location information of the IP packets of the maximum number M as in the single TX queue. Consequently, the memory resource utilizes N times as much memory, and the memory resource is wasted.